In an error checking and correcting (ECC) system, binary bit errors are detected and corrected by encoding data with check bits in accordance with a specified Hamming code. The check bits are stored in a memory and later recalled when the accuracy of the data is desired to be checked. At that time, the data is decoded and new check bits are compared with the check bits from memory in order to generate a syndrome code. From the syndrome code, the ECC system can determine if an error exists in the input data bits. ECC systems with bit slice subsystems have been implemented in LSI form with Hamming codes which allow cascading of multi-byte words. Such a subsystem has been implemented by Fujitsu Limited using an LSI ECC chip labeled MB1412A.
A problem typically results when a user of an LSI ECC system provided by a manufacturer decides to use the manufacturer's system. In such an application, the user must design his ECC system with the manufacturer's fixed Hamming code. In most cases, this puts retraints on the form which the Hamming code must take. If the user's system does not conform to the manufacturer's Hamming code, the user is forced to design his own Hamming code with SSI circuits such as parity generators unless the user manufactures his own ECC LSI chip specifically using his custom Hamming code. Since this alternative is not usually a realistic possibility, a custom design using SSI circuits is the only design choice. However, the use of SSI circuits requires much more printed circuit board space.